Intel Launches New Pentium Silver and Celeron Atom Processors: Gemini Lake is Here

Intel on Monday introduced its next-generation Pentium Silver and Celeron platform and processors. These processors are under the codename 'Gemini Lake' and are focused on low-power platforms for inexpensive desktops and mobile computers.

The new Gemini Like SoCs feature improved CPU cores over the previous generation, an enhanced media decoding/encoding engine, and a new display pipeline. Intel promises to offer higher performance than predecessors while consuming about 6 W or 10 W, depending on the application. The higher-end Gemini Lake SKUs will be sold under the Pentium Silver brand, whereas the entry-level models will carry the Celeron name.

The Platform

Gemini Lake is Intel’s third-generation low-power SoC made using the company’s 14 nm manufacturing technology. On a high level, the Gemini Lake is an evolution of the Apollo Lake launched last year, but under the hood, there is a number of differences that seem important. The relative maturity of fabrication process would be expected to allow Intel to increase transistor budget of the new chip without decreasing yields, thus enabling higher performance and a potentially an improved feature set.

Intel’s Gemini Lake SoC is based on up to four Goldmont Plus x86 cores that feature a three-wide issue architecture and supports:

1. SGX, which is required by some multimedia applications because of the latest DRM technologies,
2. SHA-NI, to speeds up cryptography,
3. UMIO, a security feature, and
4. RDPID instruction set extensions.

The GLM+ cores inside Gemini Lake SoCs are accompanied by 4 MB of L2 cache, which we believe is a last level unified cache (Intel doesn't actually confirm this), but is double from the Apollo Lake design. The enlarged cache can positively affect performance in various applications - as a rule of thumb doubling a cache cuts the miss rate by the square root of 2 (41%) at the expense of latency and power, but we don’t expect dramatic increases in performance compared to Apollo Lake across the board. The new SoCs operate at about the same frequencies as their predecessors.

Intel says that the new Pentium Silver N5000/J5005 processors are 58-68% faster than the Pentium N3540/J2900 chips (Bay Trail platform featuring the Silvermont architecture, three generations old) in SYSMark 2014 SE. The improvement looks significant, especially keeping in mind rather high clocks of the Bayview SoCs, but is not completely surprising. The older Silvermont cores features a two-wide issue architecture, were equipped with smaller caches and featured a single-channel (64-bit) DDR3 memory controller - the new Gemini Lake platform is also more energy efficient than the Bay Trail platform introduced nearly four years ago because of architectural innovations and a thinner process technology. We yet have to test the new Gemini Lake-based products ourselves to find out real-world performance benefits brought by the enlarged cache, but at this time we have to report what Intel gives us.

Video and Memory

When it comes to graphics, the Gemini Lake uses the same iGPU as Apollo Lake but with updated features: the Gen9LP core with up to 18 EUs running at 250 – 800 MHz frequency and supporting the Direct3D Feature Level 12_1 feature set. Meanwhile, the is iGPU is outfitted with the new-generation media engine found in the Kaby Lake processors that features hardware encoding/decoding of 4K HEVC and VP9 (8-bit and 10-bit) video.

It is equipped with Intel’s Gen10 display controller supporting native HDMI 2.0 output as well as the Local Adaptive Contrast Enhancement (LACE) designed to improve visibility in glare and bright light. So, while graphics performance of Gemini Lake’s iGPU is not higher when compared to the direct predecessor, the revamped media engine, LACE support and the new display pipeline allow Intel to brand it as the UHD Graphics 600-series.

As for memory sub-system, the Gemini Lake SoCs have a 128-bit memory controller that supports DDR4 and LPDDR3/4 at up to 2400 MT/s, but no longer supports DDR3L, which is an outgoing standard anyway. We are not sure that all designs will use all the memory channels, but at least it is possible to outfit a Gemini Lake SoC with a memory sub-system offering up to 38.4 GB/s of bandwidth. Furthermore, DDR4 memory support will enable OEMs to build cheaper systems based on the Gemini Lake because DDR3L (as well as LPDDR3/4) are currently more expensive than commodity DRAM.

Storage and Connectivity

Moving on to storage and connectivity. Gemini Lake supports two conventional SATA HDDs and SSDs, PCIe 2.0 x2/x4 SSDs, as well as eMMC 5.1 storage solutions. As for I/O interfaces, the new SoCs feature USB 3.0/2.0, USB Type-C, SPI, SDXC and other modern buses.

The most import important I/O-related addition to the Gemini Lake (when compared to the Apollo Lake) is the CNVi (Connectivity Integration Architecture) MAC blocks for Wi-Fi, Bluetooth and baseband modem. The addition of the CNVi is rather important because it enables Intel’s partners among OEMs to throw in a relatively inexpensive RF module that brings support for necessary wireless connectivity standards instead of buying a more expensive adapter. Since the Gemini Lake SoCs cost exactly the same amounts of money as their predecessors, the CNVi architecture enables PC makers to cut down BOM costs for at least some of their SKUs (at least, according to Intel). Unfortunately, since Intel does not disclose pricing of its CNVi RF modules and Wi-F + BT models, we do not know how significant those BOM savings might be.

For Gemini Lake-based devices Intel proposes to use the Wireless-AC 9560 product that supports 802.11ac wave2 Wi-Fi with 160 MHz channels along with Bluetooth 5.0. The Wireless-AC 9560 supports up to up to 1.73 Gbps downlink with MU-MIMO, which is why Intel is advertising Gigabit Wi-Fi in connection with the Gemini Lake. Keep in mind that not all systems based on the Gemini Lake will use the Wireless-AC 9560 since PCIe Wi-Fi controllers are perfectly supported by the new SoCs and if an OEM has a boatload of previous-gen Wi-Fi chips, it is going to use it for their upcoming PCs.

The Family

The Gemini Lake family consists of six SKUs: two Pentium Silver models and four Celeron SoCs. The Pentium Silver chips cost $161 in 1000-unit quantities, they have higher clocks as well as all four cores enabled. The new Celerons cost $107 in commercial quantities, feature lower frequencies as well as four or two cores, depending on the model.

TDP levels of Intel’s Gemini Lake SoCs remain at 10W and 6 W, respectively. Meanwhile the SDP of the mobile-class SKUs will increase to 4.8 W (from 4 W), which is important for thinner designs. Speaking of designs, it is noteworthy that the Gemini Lake SoCs use a new flip-chip packaging (FCBGA1090) and therefore are not pin-to-pin compatible with the predecessors. The new SoC form-factor will require OEMs to make new PCBs for their Gemini Lake-based systems, and because they are a bit smaller it could save space for battery.

What is noteworthy about the Gemini Lake SoCs is that CPU base frequencies have not changed compared to respective Apollo Lake SKUs and burst frequencies only increased slightly (by 200 MHz, less than 10%). Therefore, all general-purpose performance benefits that Gemini Lake may have over their immediate predecessors are going to be originated from larger caches and whatever microarchitectural optimizations the new Goldmont Plus cores may have. Certainly, new instruction set extensions will bring their benefits, but only after software starts to use them.

As for iGPU performance, do not expect Gemini Lake SoCs to offer better performance in games than their direct predecessors. Meanwhile, hardware-accelerated HEVC/VP9 media playback is a feature not to miss because of quality/smoothness and energy-efficiency improvements.

TDP levels of Intel’s Gemini Lake SoCs for desktops and mobile PCs (including notebooks, tablets, etc.) have not changed and remain at 10W and 6 W, respectively. Meanwhile, SDP of mobile SKUs will increase to 4.8 W (from 4 W), which is going to be important for thinner designs.

Speaking of designs, it is noteworthy that the Gemini Lake SoCs use the new FCBGA1090 package and therefore are not pin-to-pin compatible with the predecessors. The new package measures 25×24 mm and is smaller than the FCBGA1296 package used for the Apollo Lake SoCs (which measure 24×31 mm). The new SoC form-factor will enable OEMs to make PCBs for their Gemini Lake-based systems a bit smaller and save space for battery. Furthermore, it is logical to expect Intel to encourage PC makers to use BGA SSDs as well as eMMC storage devices with their Gemini Lake-based offerings to make them sleeker and/or install a bigger accumulator to provide a longer battery life.

The Gemini Lake platform has existed in Intel’s public plans for quite some time and the chipmaker’s platforms started to show it in their roadmaps in the middle of the year. Most of Gemini Lake-based products were slated to ship in 2018, so the formal announcement in mid-December, three weeks before OEMs show their designs at CES, comes as a surprise. Intel does not usually announce its low-power platforms for inexpensive desktops, AIOs, notebooks, 2-in-1s and tablets with fanfares, but this time Intel’s announcement can be considered as a very quiet one. Perhaps, Intel does not want to steal the thunder from its partners, or there are other reasons. But the bottom line is the company is not sharing many details and getting information about the Gemini Lake in general at this time. Perhaps, there will be more data to process at CES.

Intel anticipates the first Gemini Lake products to arrive in the first quarter of 2018, so expect major OEMs to show their Gemini Lake-based devices at CES next month and make them available a bit later.

Source: Intel

Additional 12/13:

After a few back and forth emails with Intel, we can confirm that the Gemini Lake family is built on 14nm, rather than 14+ or 14++ which are newer variations of Intel's 14nm process technologies.  Intel also confirmed the microarchitecture is a three-wide decode, the same as Goldmont, with the following execution port layout:

There are three integer ALUs, one jump port, one load port, one store port, and two general purpose FP/vector ports, so we can dispatch up to 8 instructions in a single cycle.

We're requesting more information. 

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