The Samsung Galaxy S20+, S20 Ultra Exynos & Snapdragon Review: Megalomania Devices

The Snapdragon 865 SoC: Beating Expectations

We’ve covered the Snapdragon 865 extensively over the last few months, and more recently did a performance preview of the chip on the Galaxy S20 Ultra:

• Qualcomm Announces Snapdragon 865 and 765(G): 5G For All in 2020, All The Details

• The Snapdragon 865 Performance Preview: Setting the Stage for Flagship Android 2020

• Samsung Galaxy S20 Ultra (Snapdragon 865) Quick Performance Preview: Impressive

It’s safe to say that Qualcomm managed to beat our expectations in terms of power efficiency improvements. Which is something we’ll go over in more detail in this piece as well.

At the heart of the Snapdragon 865 we find Arm’s newest Cortex-A77 CPU cores. The new microarchitecture is said to bring a 20-25% IPC improvement over its predecessors, and that’s where the new SoC derives most of its performance improvements from, as the clock frequencies of the cores are identical to that of last year’s Snapdragon 855.

Snapdragon 865 CPU Topology

One aspect where Qualcomm did improve the design is in doubling the shared L3 cache of the CPU cluster, going from 2MB to 4MB. Not only does this further improve the performance of the CPUs by allowing for more data to be cached on-chip, but Qualcomm has explained that one of the primary reasons for this was to also improve power efficiency of the SoC by reducing how often the SoC has to access the DRAM, which is a relatively power-expensive operation.

The chip still has a 3MB system level cache that serves the various IP blocks on the SoC – it’s again meant to not only improve performance but also improve power efficiency as it avoids external memory accesses. The memory subsystem here is smart and detects when to bypass this cache when there’s latency-sensitive workloads, and in general we’ll see some massive memory subsystem improvements on the part of the Snapdragon 865 in a later dedicated section.

All the CPUs being in the same cluster and cache hierarchy means that the core-to-core latencies are relatively uniform, only differing based on their frequencies and lower level cache access latencies. It’s not too much of an exciting metric here, but it’s important context to have as we’ll consider the Exynos 990’s CPU topology in just a bit.

Again, we’ve covered the Snapdragon 865 quite extensively in the above linked articles so I recommend reading them again for other details on other parts of the new chip, such as the new ISP, DSP, and GPU details. However, one aspect that’s very defining for the flagship Qualcomm chipset this year is that the company is separating the modem from the SoC – essentially making the SoC just an application processor for this generation.

The external nature of the X55 modem has a few implications: first of all, there’s an additional component on the motherboard which vendors will have to make space for, which means additional cost. Secondly, there’s the big question of how power efficiency will be affected by the external modem. We’ve seen Apple devices perform excellently over the years while never having an integrated modem, and I feel like the Snapdragon 865 and X55 also fall into this classification, as I haven’t seen any major differences in efficiency due to the external nature of the modem.