IDF Fall 2006 - Day 2: Opteron vs. Xeon, SSE4 & Intel's Torrenza competitor Announced

Intel Follows AMD's Lead, Again: Cloning Torrenza

In another example of a string of Intel following AMD's lead, Gelsinger announced extending Intel's FSB license to FPGA manufacturers like Xilinx so that companies can produce other chips that can work alongside Intel processors with a direct FSB connection to the MCH. This should sound a lot like a less elegant implementation of AMD's Torrenza initiative; as you may remember, Torrenza is the platform standard that AMD introduced to allow other, non-AMD processors (or accelerators) to be installed in standard Opteron sockets through licensing and use of the coherent Hyper Transport specification. Intel's FSB licensing will also allow various accelerators to be plugged into a high bandwidth, low latency (potentially cache coherent) bus that would connect directly to the MCH in an Intel system.

This device somehow implements Intel's FSB license

Intel also announced work with IBM to create an extension to PCI Express, codenamed Geneseo that would be used as a higher bandwidth, lower latency interface for everything from graphics cards to physics accelerators. Gelsinger threw up a slide that showcased the broad industry support for creating products that would work with the Geneseo interface. Notable members of the alliance are NVIDIA and AGEIA for its PhysX card, indicating that Intel's thinking is similar to AMD's in that there could be a future for physics accelerator cards or even a higher speed, lower latency interconnect for GPUs that would utilize this interface. Note the absence of ATI from the list of partners supporting Intel's efforts.

Effectively, what Intel is hoping to do is gain momentum and industry support for an alternative to AMD's Hyper Transport for use with various 3rd party accelerator cards. Since Intel is unlikely to embrace Hyper Transport and AMD's Torrenza's initiative, simply extending PCI Express with additional focus on creating a higher bandwidth, lower latency version of the bus for these accelerator cards with the help of the rest of the industry (except AMD) is the next best option.

Intel expects to iron out a specification in the next 1 - 1.5 years, and the first products will be available in the coming years after that. Obviously, AMD has a much larger head start in this area and we're interested to see how things pan out given AMD's timing advantage and industry support for Hyper Transport.

IBM came on stage to talk about some of the things Intel and IBM focused on in developing the spec for the new Geneseo interface spec for 3rd party accelerators to communicate directly with the MCH in a system. The information that was shared was vague at best, but the animations during the presentation give you an example of a usage model Intel is looking at with its Torrenza-like platform approach.

Based on the vague comments by IBM, it looks like these accelerators running over the Geneseo interface could be cache coherent, support reordering of memory requests in order to prioritize the most important requests and able to be power managed must like any other component in the system.